In the design of integrated circuits, it is often desirable to create, as part of the design, devices having a fixed ratio of some of their characteristics. Here, the term “devices” refers to circuit elements such as transistors, capacitors, etc. . . . To achieve the required performance of the circuit, it is often necessary to manufacture this ratio to a very high degree of accuracy compared with the designed-for value. Deviations from this ratio can lead to offset or linearity errors.
If this ratio is an integer or a rational number then the devices are usually constructed using the appropriate number of unit elements. For example, to create two devices with a ratio of 2/3, five equal unit elements are created and three unit elements are assigned to one of the devices and two unit elements to the other one. This eliminates secondary device effects which are dependent on the actual device geometry as opposed to on the area alone.
However, the manufacturing process for semiconductor chips produces artifacts in nominally equal devices. These artifacts include both systematic variation for all devices of a particular type on a single chip or wafer as well as random variations between individual devices on a single chip. These latter random variations, called mismatch, disturb the nominally equal nature of the devices. For example, referring to the example above of using five unit elements for implementing two devices with a 2/3 ratio, random variations in the dimensions of the unit elements may result in the ratio of the two devices deviating from the desired 2/3 ratio.
A technique called “dynamic element matching” (DEM) exists that can ameliorate this mismatch. In DEM, the different elements used to implement devices having a desired ratio are rotated through different positions in the system over time, so that the time average of the device ratio will be substantially closer to the ideal value. For instance, in the example of using five unit elements to create the ratio 2/3, ten different combinations of the elements may be used to implement the two devices having the 2/3 ratio. The average of these ten combinations will lead exactly to the ideal ratio 2/3, even with deviations for each of the individual combinations stemming from random variations in the five unit elements.
During operation, the elements are cycled through each of the possible configurations in sequence, and the elements are activated in each configuration to generate a sample analog signal. The sample analog signals from each combination of elements in the sequence are output to a signal processing system, such as an ADC. Due to mismatch, each configuration of elements generates a sample analog signal having a slightly different value. The ADC averages the sample analog signals to arrive at a digital output value for use in subsequent digital signal processing.
To allow DEM to mitigate the effects of device mismatch, the sample analog signals generated by each configuration of elements must contribute with the same weight to the final output result. Such a system is referred to herein as a “system with constant weights.” One type of system that uses constant weights is a first order resettable sigma-delta ADC, sometimes called a first order incremental ADC. An incremental ADC is an oversampling ADC that is configured to convert a plurality of samples of an analog signal into a digital bit stream using a resettable analog accumulator and thus is particularly suited for processing analog signals generated using DEM.
A block diagram of an example of a first order incremental ADC 100 is shown in FIG. 1. During operation of the ADC 100, the sample analog signals generated by the different element configurations are input to the integrator 104. The output of the integrator 104 is converted into a digital value by an ADC 108. The output of the ADC 108 is provided to a digital integrator 110, which operates as a digital filter to generate the output 3040 for the ADC 100. The output of the ADC 108 is also fed to a digital-to-analog converter (DAC) 114 in the feedback path of the ADC 108. The DAC 114 outputs an analog signal that is added to the input signal at the summing node 118.
The integration on this composite signal by the integrator 104 moves the signal noise into the high frequency components of the integrator's 104 output. After conversion of the integrator's output by the ADC 108, the digital filter 110 operates as a low pass filter, which removes the high frequency components, including the noise. In particular, the digital filter 110 is configured to implement a first order transfer function, also referred to herein as a weighting function, for integrating, or averaging, the samples to generate the digital output. In the averaging implemented in a first order incremental ADC, each sample contributes with the same factor or weight to the final result. Thus, the weight at which each sample in a plurality of samples contributes to the final result is (1/S). If the total number of samples used to calculate the output value is ten, then the weight allocated to each sample is 1/10, or 0.1 as depicted in the graph of FIG. 2.
If conventional averaging takes place, such as in a first-order incremental ADC, cycling through each of the possible combinations of elements reduces the effect of unit element mismatch. For a system implemented using a number N of unit elements having a number M of possible configurations in the system, a cycling sequence may be denoted as i, where iε{1, 2, . . . , M}. If the required number of samples to make a conversion is greater than the number of combinations, the sequence i is repeated until the required number of samples has been collected. In a first order incremental ADC, the same weight is allocated to each sample for the computation of the average regardless of the number of samples utilized. Since an equal weight is allocated to samples generated by each combination, mismatch between the combinations is averaged. For example, if each of the M combinations has a random variation Δi for iε{1, 2, . . . , M}, then the final result has a random variation equal to
      1    M    ⁢            ∑                            ⁢                  Δ        i            .      Accordingly, if the sequence of combination of elements consists of all possible combinations of these unit elements, than this averaging will lead to the random variations effectively canceling each other out so that the final result will have no random variation.
One disadvantage to the use of first order incremental ADCs for analog signal processing, however, is a relatively slow conversion time. For example, for n-bit resolution, the ADC needs 2n integrations, or clock periods, for each conversion cycle resulting in a very slow conversion rate in relation to the ADC's clock frequency. Conversion times may be made faster by increasing the order of the incremental ADC. The order level of the ADC refers to the total number of integrators in the ADC. For example, for the first order incremental ADC shown in FIG. 1, a single integrator 104 is provided; a second order incremental ADC has two integrators; a third order incremental ADC has three integrators; etc.
In second order and higher incremental ADCs, however, the weights allocated to the samples are not equal. If the same DEM cycling scheme iε{1, 2, . . . , M} is used, then the random variation, Δi, of each sample at the output of the ADC is given by
      2          M      ⁡              (                  M          +          1                )              ⁢            ∑                            ⁢          i      ⁢                          ⁢                        Δ          i                .            Consequently, the random variation of each sample does not contribute equally to the average and the output has a much higher residual variation relative to a first order incremental ADC. The residual variation increases with the order of the incremental ADC.
Accordingly, what is needed is a sensor and/or a method of operating a sensor in which the sample analog signals output by the sensor are suitable for processing by a system with non-constant weights, such as second order and higher incremental ADCs. In particular, what is needed is a second order dynamic element rotation scheme for sensors that enables second order and higher incremental ADCs to be utilized for integrating and converting the sample signals into a digital output with a lower residual variation relative to previously known schemes.